USP 51系列仿真器
Wide range of pods to emulate virtually all 8051
family members from Atmel, Dallas, Infineon, Intel,
OKI, Philips, TDK, TI and Winbond
- Real time transparent emulation up to 60 MHz
- HLL debug for C-51, PL/M-51 and ASM-51
- Up to 256K of overlay Program RAM with bank
switching
- Up to 64K of overlay External Data RAM
- Memory (Code and Xdata) display and edit while
executing in real-time
- In-line symbolic assembler and disassembler
- Memory mapping (User or ICE) on 256 byte boundaries
- Up to 256K of real-time hardware breakpoints
which work in RAM, ROM, EPROM and Flash
- 32K frames (80 bits wide) of execution Trace
Buffer with time stamp on each executed instruction
and selective tracing
- Trace display during execution
- Pass-points to monitor IRAM, locals and SFRs
while running
- Breakpoints on Register and internal RAM values
- Complex Events to trigger Breakpoints or Trace
logic
- Two 16 bit Pass Counters for breakpoints and
trace control
- 8 level hardware event Sequencer for breakpoints
and trace control
- 8 channel user logic state analyzer to display
misc. signals in trace
- All Complex Events can trigger external Logic
Analyzers and Scopes
- External Break input to stop the CPU from external
sources
- Performance Analysis with histograms for execution
speed analysis
- Execution Profiling with bar graph for function
frequency analysis
- Coverage Analysis with source tagging and report
of unexecuted code
- Windows 2000 / NT4 / 98 / ME / XP user interface
- Serial or parallel port interface to the host
PC
- emote debugging over TCP/IP network
- Virtual Prototyping Environment, VIPER
USER INTERFACE
Designed to work with IBM PC computers, the
8051 Windows user interface provides: multiple
Source, Registers, Memory, Stack, Variables,
Locals, Performance, Trace and other pop-up
windows; source level debugger window for C-51
and PL/M-51 with automatic link to the Trace
window; user defined variables in the Watch
window.
DUAL-PORTED MEMORY
This unique feature allows instant viewing and
modification of emulation memory (Program and
Data) without stopping or slowing down the running
8051 application.
COMPLEX EVENTS
Through its Setup window, the 8051 emulator enables
you to graphically program the three available
complex events and to define how these events
will be used for breakpointing and trace filtering.
Each event is capable of comparing in real-time
the address bus, data bus, and cycle type. This
can be used, for example, to detect the writing
of values between 44 and 55 to one or more specified
locations in memory. Once a complex event is defined,
it may be passed to one of the two available 16-bit
counters to create a delayed breakpoint or trace
trigger. With the use of the 8-level sequencer
any combination of events and counters may be
mixed to achieve a trigger based on a predetermined
sequence of events.
BREAKPOINTS
Breakpoints are used to stop user program execution
while preserving the current program status.
8051 breakpoints can be triggered from a combination
of:
Addresses and address ranges
Complex Events
- Register values and internal RAM
- External input
- Pass Counters
- Sequencer
- Trace full condition
TRACE BUFFER
Trace buffer is a high speed RAM used to capture
in real time all activity on the 8051 microprocessor
bus and pins. A dedicated start/stop logic allows
for filtering out unwanted information from
the trace buffer while executing. Trace will
store up to 32 K samples (80-bit frames) comprised
of the following:
- Address Bus
- Data Bus
- Control signals (RD. WR, Fetch, IRQ)
- P0, P1, P2, P3 (P4/P5 if avail.)
- Real Time Clock Stamp
- User logic state inputs (8 bits)
- The 8051 trace may be filtered before the
information is stored with the use of complex
events, and after the acquisition by choosing
the filter menu. The trace is equipped with
an internal counter to allow tracing to stop
after a specified number of frames have been
captured. This feature allows the trace to capture
as much as 32K of small program fragments no
matter how distant in time. The trace contents
can be viewed during program execution without
stopping or slowing down the 8051 microcontroller.
LAN SUPPORT AND REMOTE DEBUGGING
All Signum 8051 emulators support operation
over a network. The IceServer option allows
you to work with any ICE connected to a networked
computer from any workstation on the network.
You can also connect to any Chameleon debugging
session using a standard telnet terminal session.
This allows you to join a remote debugging session,
for example, to take a peek at what is happening
in the lab or at a test site.
8051 EMULATOR SPECIFICATIONS
- Suported Microcontrollers
Atmel/TEMIC
AT89C51, AT89C52, AT89LV51, AT89LV52
AT89LS51, AT89LS52, AT89LS53,
AT87F51, AT87F51RC, AT89F52
AT89C1051, AT89C2051, AT89C4051
AT89S8252, AT89LS8252, AT89LV55
AT89C51ED2, AT89C51IC2, AT89C51ID2, AT89C51RB2,
AT89C51RC, AT89C51RC2, AT89C51RD2
TS80C31X2, TS80C32X2, TS87C52X2, TS87C54X2,
TS87C58X2
TS89F51RA2, TS89F51RB2, TS89F51RC2, TS89F51RD2,
TS87C51U2
T89C51CC01, T89C51CC02, T89C51CC03
T87C5101, T87C5111, T87C5112, T89C5115
T89C5131 (USB device)
Dallas Semiconductor
80C310, 80C320, 87C520, 87C530
Infineon/Siemens
80C515, 80C535, 87C515A, 87C517A, 80C537
C501, C505CA (CAN device)
Intel
80C31, 80C32, 87C51, 87C52, 87C54, 87C58, 87C51FA/FB/FC,
87L52, 87L54, 87L58, 87L51FA/FB/FC
OKI
80C31, 87C51, 87C154
Philips
80C31, 80C32, 8xC51, 8xC52, 80CL31, 80CL32,
8xCL51, 8xCL52, 8xC51FA, 8xC51FB, 8xC51FC, 8xC51RA+,
8xC51RB+, 8xC51RC+, 8xC51RD+, 8xCL410, 8xC451,
8xC524, 8X528, 8xC550, 8xC552, 8xC562, 8xC575,
8xC576, 8xCL580, 8xC652, 8xC654, 8xV748, 8xC749,
8xC750, 8xC751, 8xC752, 8xC781, 80C851
87C51RA2, 87C51RB2, 8xC51RC2, 8xC51RD2 (with
clock doubler)
TDK Semiconductor
K246, 73D2910, 73D2912, 73D2918, 73M2910L/2909
73S1121/1111/1112
Texas Instruments
TUB3200
Winbond
W78C32, W78C33, W78L32, W78L33, W78C51, W78C52,
W78C54
W78L51, W78L52, W78L54, W78E51, W78E52, W78E54,
W78E58
W78E858, W78LE51, W78LE52, W78LE54
- Maximum emulation speed
20 MHz, 40 MHz or 60 MHz
- Size
260 mm wide, 260 mm deep, 64 mm high
- Max. Emulation Program Memory
64 Kbytes standard, 256 Kbytes optional
- Max. Emulation External Data Memory
64 Kbytes
- Program Memory mapping
256 byte boundary
- Data Memory Mapping
256 byte boundary
- Pass Counters
Two, 16 bit each, with Stop/Reload control
- Trace buffer
32 K deep, 80 bits wide with filtering control
- Real-Time Time Stamp
32-bit, 100 ns resolution with Absolute, Relative
and Delta modes
- Sequencer
8 level hardware
- User probe
8 channel logic input, 1 trigger input, 6 trigger
outputs (Events, Pass Counters, Sequencer)
- Host interface
Parallel (LPT1-LPT2)
Serial RS-232C (COM1-COM4), 9600-115 KBaud
- File upload/download format
Intel HEX, Intel AOMF, Archimedes, IAR, Franklin,
Keil, Raisonance, Tasking and others
ASIC 8051 SUPPORT
-
If you need to debug your 80C51 core based ROM-less
80C51 derivative or ASIC, but cannot physically
remove the device from the system, POD51-ASIC
is a perfect solution. This pod employs the
80C51 CPU core on the target PCB (or inside
the ASIC device) in lieu of the conventional
method of using the emulated CPU for in-circuit
emulation. This effectively eliminates the need
to remove the CPU/ASIC from the target board
to perform non-intrusive real-time emulation!
The pod provides all emulation objects, such
as memorySome of the POD51-ASIC features:
Supports any ASIC with embedded 2.5-5V 8051
core
- TDK 73S1121/1111/1112 at up to 66 MHz
- Intel standard 12-clock core architecture
- Atmel/Philips 6-clock core architecture
- Dallas type core architecture
- other architectures (please inquire )
- Works with Signum USP-51A emulator
and Chameleon Debugger
- Reprogrammable (FPGA) and customizable
- Small, high-density (.5 mm pitch) connector
- Small and lightweight design (3.0 ?2.8 in.)
|
